1. Field of the Invention
Example embodiments of the present invention are generally related to an optical proximity correction (OPC) system and methods thereof, and more particularly related to an OPC system and methods of adjusting an integrated circuit (IC) layout to generate a mask pattern.
2. Description of the Related Art
Lithography technology used for fabricating semiconductor devices may employ a process of transcribing a pattern, which may be formed on a photomask through an optical lens, onto a wafer. With increasing integration density of semiconductor devices, the dimensions of mask patterns may approximate wavelengths of light, such that the lithography process may be increasingly affected by diffraction and interference of light.
FIG. 1A illustrates a conventional mask pattern. FIG. 1B illustrates a conventional photoresist pattern formed by the mask pattern of FIG. 1A. A review of FIGS. 1A and 1B may reveal that as optical systems projecting light function as low-pass filters, photoresist patterns arranged on wafers (e.g., FIG. 1B) may be distorted from their “original” mask patterns (e.g., FIG. 1A).
Because a spatial frequency may be lower if a mask pattern is larger in size or is transferred with a higher number of repetitions, many different frequencies may be capable of transmitting the mask pattern, resulting in a structural pattern which may approximate an original mask pattern onto a wafer. However, generally, portions of higher frequencies may cause pattern distortions in “roundish” shapes. Such pattern distortions may be caused by an “optical proximity effect” (OPE). Because the spatial frequency may increase as a pattern size is reduced, the number of frequencies permissible to transmit the reduced pattern may decrease such that the pattern distortion due to OPE may likewise become more severe.
Optical proximity correction (OPC) may at least partially reduce pattern distortion due to OPE. OPC may involve adjusting an expected pattern distortion by intentionally altering an original mask pattern. OPC may improve an optical resolution and a pattern transfer fidelity. A conventional OPC process may include adding or removing small patterns, which may typically be less than the designed resolution, to or from a mask pattern associated with the photomask (e.g., line-end treatment or insertion of scattering bars).
FIG. 2A illustrates a line-end treatment during a conventional OPC process. As shown in FIG. 2A, a line-end treatment may include adding corner serif or hammer patterns to an original mask pattern in order to reduce “roundish” or rounded patterns of line edges.
FIG. 2B illustrates a scattering bar insertion during a conventional OPC process. As shown in FIG. 2B, scattering bar insertion may be conducted by adding sub-resolution scattering bars around target patterns in order to reduce variation of line widths by pattern density.
After a photolithography processing technique, design rule checking (DRC), an electrical rule checking, electrical parameter evaluation (EPE), and the process of layout-versus-schematic (LVS) according to checking and evaluation operations, and a layout process may be performed. Further, an additional step of intentionally altering a layout pattern using an OPC process may be performed.
OPC processes may be generally classified as a rule-based process processing layout data (e.g., employing rules established by a number of lithography engineers), and a model-based process correcting a layout configuration based on a mathematical model of the lithography system.
The conventional rule-based process may be carried out by altering or adjusting a layout based on one or more rules, such as partially cutting away primitive patterns and/or adding subsidiary patterns thereto. The rule-based process may be performed relatively quickly because the layout data corresponding to the entire chip area may be affected at a given time. However, it may be difficult to establish valid rules to employ during the rule-based process (e.g., rules which work effectively for any number of possible mask transfers). For example, a tedious process of experimental trial and error may be performed in order to establish the rules. Further, the trial and error process may continue indefinitely as new rules are employed to further optimize the system.
The model-based process may be conducted by correcting deformation of mask patterns by applying a model of lithography system to a negative feedback system. Based on repetitive calculation, the model-based process may consume a significant amount of time and processing power to simulate a relatively small amount of data. However, the model-based process may be more likely than the rule-based process to eventually arrive at an “optimized” solution for the OPC process irrespective of a configuration of pattern. The model-based process may arrive at an acceptable solution even if no rules have been previously established (e.g., via the rule-based process), and further may be used to find a rules for an application of the rule-based process. Accordingly, acceptable mathematical solutions may be obtained for various mask patterns with less actual experimentation (e.g., and more simulations). As a result, if time and expense is not a factor, lithography engineers may employ the conventional model-based process for patterning memory cells.
The conventional model-based OPC process may include generating a mask layout corresponding to the shape of a pattern selected on based on a given OPC model after dividing a layout pattern of an integrated circuit (IC) into a plurality of fragments. However, the given OPC model may typically not model particular shapes of selected patterns and the features of dispositions with peripheral patterns. For example, if a single OPC model is applied to an entire layout (e.g., to each of the plurality of fragments), it may be difficult to accomplish an optimum pattern correction because fluctuations or subtleties in the layout (e.g., the shapes and dispositions of patterns) may generally be ignored in favor of the more idealized or theoretical OPC model (e.g., the OPC model may not be “fine-tuned” for each of the fragments).
FIG. 3 is a graphic diagram showing gaps of fitting errors according to pattern architecture appearing through a conventional OPC process. FIG. 4 is a graphic diagram showing fitting errors of a conventional OPC process employing a single OPC model.
As shown in FIGS. 3 and 4, although an OPC model may be applied thereto in accordance with the conventional scheme, fitting errors may be different from each other in uniformity by the structures of patterns. For example, the line-end structure 10 may include a larger distribution profile of fitting errors, due to a concentration by OPE thereon, than that of a line-and-space or block structure.
Referring to FIGS. 3 and 4, a large distribution profile of fitting errors may make the model-based OPC process difficult to apply usefully within a higher-density semiconductor device.
FIG. 5 illustrates a portion of the pattern architecture that may not be fixed by the conventional OPC process.
Referring to FIG. 5, a semiconductor device may be fabricated including a line-end pattern 21, and peripheral patterns 22 adjacent to the line-end pattern 21. As intervals between the patterns become narrower along more highly integrated semiconductor devices, the conventional OPC process, having a relatively high distribution profile of fitting errors, may be insufficient for the structure shown in FIG. 5. As aforementioned, the large fitting-error distribution profile associated with the conventional OPC process may be at least partially based on an associated OPC model incapable of taking into consideration a selected pattern and/or a disposition structure of peripheral patterns around the selected pattern. Further, the conventional OPC process may not take into consideration various illumination characteristics (e.g., off-axis illumination), which may be associated with higher integration of semiconductor devices.